The invention relates to a memory sense amplifier for amplifying a data signal read from a memory cell matrix.
Semiconductor memories are binary data memories having a semiconductor memory cell matrix in which the individual memory cells are arranged in matrix form and comprise the semiconductor components. In this case, the individual memory cells are connected to word lines and to bit lines running perpendicularly thereto. The addressing, i.e. the selection of a memory cell or of a memory word is effected by the activation of the word lines and, in the case of a bit selection, by selection of one of the bit lines BL. The addressing is effected via an address decoder which generates selection signals for word line and/or bit line selection in a manner dependent on an address signal present on an address bus. The data signals read out are read out via a sense amplifier which amplifies the data signal read out.
FIG. 1 shows the basic construction of a semiconductor memory having a memory cell matrix which is addressed via an address decoding circuit and which outputs read-out data signals to a sense amplifier integrated in the semiconductor memory. The sense amplifier comprises a plurality of sense amplifier units which each amplify a data signal present on a bit line BL.
FIG. 2 shows a sense amplifier unit according to the prior art.
In the reading operating mode, the voltage which is present on the bit line BL and the bit line {overscore (BL)} complementary thereto and forms the data signal that is read from the memory is amplified by a differential amplifier circuit and is output at the signal output OUT. In this case, the differential amplifier is constructed symmetrically and comprises two PMOS transistors P1, P2 and also two NMOS transistors N2, N3. The differential amplifier is activated by the application of a control signal S, which turns on the NMOS transistor N4.
After the read operation, the bit lines BL and {overscore (BL)} must be charged again uniformly. This is done by the two NMOS transistors N0, N1, the PMOS transistor P0 connected in parallel therewith being turned on and equalizing the voltage potential built up in each case on the bit lines BL, {overscore (BL)}.
The voltage VBL to which the bit lines are charged via the two NMOS transistors N0 and N1 is:
VBL=VDDxe2x88x92VTHNxe2x80x83xe2x80x83(1) 
where VDD is the supply voltage and VTHN is the threshold voltage of the NMOS transistors N0, N1 at a source-substrate voltage of 0 volts.
On account of the substrate effect or body effect, the threshold voltage of a MOSFET transistor depends on the source-substrate voltage.
VTH=VTH0+xcex2*VSBxe2x80x83xe2x80x83(2) 
where xcex2 is a technology-dependent constant and VSB denotes the voltage between the source terminal and the substrate terminal (bulk).
The charging current I depends on the voltage difference between the gate-source voltage Vgs and the threshold voltage VTH.
I=K*(Vgsxe2x88x92VTH)xe2x80x83xe2x80x83(3) 
where K denotes a constant which is dependent on the fabrication technology and the dimensions of the MOSFET transistor.
The substrate voltage VB and also the source voltage VS are usually zero volts, so that the difference voltage VSB is likewise zero volts and the substrate effect is not manifested. As soon as a voltage difference that deviates from zero occurs between the source and the substrate terminal VSB, the threshold voltage VTH increases and the charging current I decreases. At the same time, the charging voltage VBL applied to the bit line decreases.
VBL=VDDxe2x88x92VTH0xe2x88x92xcex2*VSBxe2x80x83xe2x80x83(4) 
If the voltage VS present at the source terminals of the two NMOS transistors N0, N1 reaches the charging voltage value VBL=VDDxe2x88x92VTH, the current flowing through the NMOS transistor is approximately:
I=K1(VDDxe2x88x92VTHxe2x88x92V3)2xe2x80x83xe2x80x83(5) 
The negative consequences of the substrate effect are amplified the higher the degree of miniaturization of the fabrication technology. The threshold voltage deviation increases greatly in particular in the case of fabrication technologies with dimensions far smaller than 1 xcexcm, i.e. 0.25 xcexcm, 0.18 xcexcm or less. Since the technology-dictated constant xcex2 cannot be set exactly, the precharge voltage VBL occurring on the bit line BL likewise fluctuates to a great extent. It is not possible, therefore, to ensure a predefined precharge voltage on the bit lines.
A further disadvantage of the precharge circuits comprising the NMOS transistors N0, N1 and serving for charging the bit lines BL, {overscore (BL)} of the conventional memory sense amplifier unit illustrated in FIG. 2 is that the charging time required for charging the bit lines is relatively long on account of the substrate effect. Since a charging operation of the bit lines BL, {overscore (BL)} is necessary between every reading and writing operation for reading data from the memory and for writing data to the memory, overall the memory access time is considerably increased as a result of this.
The object of the present invention, therefore, is to provide a memory sense amplifier unit which ensures a minimal charging time for charging the bit lines to a specific voltage potential.
This object is achieved according to the invention by means of a memory sense amplifier unit having the features specified in patent claim 1.
The invention provides a memory sense amplifier unit for amplifying a data signal read from a memory via bit lines, having a precharge circuit comprising PMOS transistors and serving for rapidly precharging the bit lines to the supply voltage potential of the memory sense amplifier unit, a first amplifier stage comprising feedback NMOS transistors and serving for voltage level shifting and for amplifying the data signal present on the bit lines; and having a second amplifier stage for amplifying further the signal output by the first amplifier stage, in which case the first amplifier stage (43) can be initialized to the supply voltage potential (VDD) and the second amplifier stage (43) can be initialized to ground potential (VSS).
One advantage of the memory sense amplifier unit according to the invention is that it compensates for the substrate effect. Consequently, the memory sense amplifier unit according to the invention is suitable in particular for fabrication technologies with structural dimensions smaller than 1 xcexcm.
A further advantage of the memory sense amplifier unit according to the invention is that it functions even at a relatively low supply voltage.
In a preferred embodiment of the memory sense amplifier unit according to the invention, the precharge circuit switches the supply voltage potential through directly, without a voltage drop, to the bit lines, in a manner dependent on a first operating mode control signal present at the gate terminals of the PMOS transistors.
The first amplifier stage preferably shifts the voltage potential present on the bit lines by a constant voltage value.
The first amplifier stage preferably comprises four feedback NMOS transistors.
The second amplifier stage is preferably a differential amplifier stage comprising two PMOS transistors and two NMOS transistors.
In a preferred embodiment, the sense amplifier unit according to the invention can be changed over between a precharge operating mode, a writing operating mode and a reading operating mode by two operating mode control signals.
In this case, in the precharge operating mode, the sense amplifier unit is preferably initialized for a subsequent read/write operation.
In a preferred embodiment of the sense amplifier unit according to the invention, the second amplifier stage can be connected to ground by means of an NMOS transistor, the NMOS transistor being controlled by the second operating mode control signal.
This NMOS transistor is used for activating and deactivating the second amplifier stage in order to reduce the energy consumption when the reading operation is not being performed.
In a further preferred embodiment of the sense amplifier unit according to the invention, the gate terminals of the two PMOS transistors of the second amplifier stage can be connected to a ground potential by means of pull-down transistors which are driven by the inverted second operating mode control signal.
The supply voltage is preferably connected to the first amplifier stage by means of a PMOS transistor, the PMOS transistor being driven by the inverted second operating mode control signal.
In a particularly preferred embodiment, the memory sense amplifier unit is constructed using CMOS technology.